RAM Hardware

RAM Hardware

Jan 31, 2022 10:22 PM

Today, I learned more about RAM from a hardware perspective from:

The two main types of RAM are static RAM (SRAM) and dynamic RAM (DRAM). SRAM is faster but is much more expensive than DRAM. Why is that?


DRAM cells consists of one transistor and one capacitor to store the electrical signal. Below are some disadvantages of DRAM:

  • Memory cells need to be refreshed at certain intervals (typically 64ms) since capacitors slowly leak their charge and lose their value. During the refresh cycle, memory can’t be read or written to.
  • The capacitors store tiny charges and to actually read the 0 or 1 from it, the charge needs to be amplified by a sense amplifier. This increases memory access latency for each read and write operation and affects total bandwidth as well.
  • Every time a memory cell is read, the capacitor storing the value loses its value and needs to be re-written back to the memory cell.
  • The sense amplifier doesn’t output a rectangular signal so an estimate over time has to be used.

So why do people still use DRAM instead of SRAM?

  • DRAM is smaller
  • DRAM is cheaper


SRAM requires six transistors per cell and constant power to maintain the correct value in the cell. The advantages of SRAM include that it is available for reading almost instantly and no refresh cycles are needed.

  • Doesn’t have the same delay as DRAM does to read data since the data is available immediately. SRAM doesn’t need to wait for a capacitor to discharge and the sense amplifier to amplify the charge in the capacitor. SRAM memory latency is much lower.

DRAM Access

Before reading this section, it’s probably a good idea to watch this lecture series on DRAM: https://www.youtube.com/watch?v=I-9XWtdW_Co

A program selects a memory location of a virtual address. The processor translates this into a physical address and the memory controller selects the RAM chip corresponding to that address. The memory cell is chosen by passing data on the control bus address lines.

To specify a specific address, there are 32 lines (on a 32-bit machine) and the memory cell that is accessed is represented as a binary number which is demultiplexed to identify the memory cell. As the memory size gets larger, this becomes infeasible because there are more address lines to synchronize with the clock and exponentially more select lines. To alleviate this problem, memory is organized into rows and columns so that the number of select lines is reduced by half. However, the most costly part of memory is the number of address lines the memory has. Sometimes, the address lines will be cut in half and transfer the row and column information in separate cycles. This reduces the cost at the expense of bandwidth over the address lines bus.

Once a processor decides it wants to read memory, the memory controller makes the row address of the memory available on the address bus. It lowers the RAS signal and the RAM chip selects the address row. Next, the CAS signal is sent on the next clock cycle (+ some delay called the RAS to CAS delay) and that is read by the RAM chip. After some time, the data is ready to be transmitted. The RAM chip needs some time to do this; this time block is known as CAS latency.

To reduce the fixed cost of these latencies, DRAM modules allow the memory controller to specify how many words are transmitted in one read access. The memory controller can also send multiple CAS signals while keeping the row pre-selected to send consecutive memory addresses.

There are a couple delays that are notable in memory hardware:

  • CAS Latency: latency between the column address being sent on the lines and when the data begins to transfer
  • RAS-to-CAS delay: latency between when the row address is sent and the column address is sent
  • RAS Precharge delay: latency between when the data is first sent and it takes for the row to precharge. No new row address can be sent till this is ready and all the data has been transferred.
  • RAS-to-RAS delay: latency between RAS signals before it can precharge another row. This value is typically pretty high.

DDR modules are typically described using the following notation: w-x-y-z-T:

  • w: CAS latency
  • x: RAS-to-CAS delay
  • y: RAS Precharge delay
  • z: Active to Precharge Delay
  • T: command rate

Example: 2-3-2-8-T1

These values can generally be tuned in the BIOS, but be warned, this may overclock the hardware and put it at risk.